Field of Invention
The present invention relates to a semiconductor structure and a manufacturing method of the semiconductor structure.
Description of Related Art
A conventional semiconductor structure may include a chip, an electrical pad, a dielectric layer (e.g., SiO2), a redistribution layer (RDL), a conductive layer, a passivation layer, and a solder ball. In general, when the semiconductor structure is manufactured, the dielectric layer is used to cover a silicon substrate (i.e., a wafer) which is not divided yet to form plural chips, so as to protect electronic components (e.g., a light sensor) on the semiconductor structure. Thereafter, a photolithography process and an etching process may be used to remove the silicon substrate and the dielectric layer above the electrical pad that is in the dielectric layer, such that a through via is formed in the silicon substrate and the dielectric layer, and the electrical pad is exposed through the through via.
Subsequently, an isolation layer may be used to cover the surface of the silicon substrate facing away from the dielectric layer and the surface of the silicon substrate surrounding the through via. After forming the isolation layer, the redistribution layer and the conductive layer may be sequentially formed on the isolation layer and the electrical pad. After the conductive layer is formed, the passivation layer may cover the conductive layer, and an opening is formed in the passivation layer to dispose the solder ball.
However, since the conductive layer completely covers the redistribution layer, the material of the conductive layer (e.g., nickel and gold) is wasted. Moreover, after the solder ball is in electrical contact with the conductive layer, the fixity of the solder ball needs to be test by a lateral force (i.e., a shear force). Because the conductive layer completely covers the redistribution layer, when the solder ball receives the lateral force, corners of the redistribution layer and corners of the conductive layer are easily damaged, and thus the yield rate of the entire semiconductor structure is difficult to be improved.
Furthermore, the slope of the surface of the silicon substrate surrounding the through via is steep. That is to say, a via aspect ratio (depth/width) is large. Hence, the breaks of the redistribution layer and the conductive layer are prone to occur at the turning point of the silicon substrate adjacent to the through via, such that the yield rate of the semiconductor structure is difficult to be improved. Moreover, in order to reduce the via aspect ratio, although thin silicon substrates may be used to manufacture the semiconductor structure, thick silicon substrates cannot be used, which is an inconvenient factor for designers.